Forty years of electronics education is written in SPICE. Textbook appendices, course handouts, application notes: the circuits are all there, as terse netlists that describe everything except what a breadboard should look like. de:volt now closes that gap on every plan, free: File → Export… → Import SPICE netlist takes a .cir, .net, or .sp deck and rebuilds it as a real, placed, wired board.

A netlist in, a board out

Save this classic as rc.cir (any text editor):

RC low-pass demo
V1 in 0 SIN(0 1 1k)
R1 in out 1k
C1 out 0 100n
.end

In the simulator, open the Export dialog, choose Open file… under Import SPICE netlist, and pick the file. The importer parses the deck, places a breadboard, and builds the circuit: a source feeding in, a 1 kΩ resistor from in to out, 100 nF from out to ground. Values come through exactly as written, supply and ground nets route to the board's rails, and the whole thing is ordinary editable parts afterwards: swap the resistor, drag the layout, probe everything.

Press Run, put the scope on in and out, and you have the RC low-pass response live: at 1 kHz drive with a 1.59 kHz corner, out sits visibly attenuated and phase-shifted behind in. The netlist said what; the breadboard shows how.

What carries over

The importer maps each device type onto one predictable catalog part: resistors, capacitors, inductors, diodes, NPN and PNP transistors, MOSFETs, N-channel JFETs, and the usual sources. A DC V card arrives as the Bench PSU, PULSE as the Pulse Generator, SIN as the Signal Generator with amplitude, offset, and frequency filled in. Values come through exactly as written; identity is deliberately defaulted, because a netlist says "r1 1 2 1k" without saying which resistor, and guessing a specific part from a .model card would be right sometimes and silently wrong the rest of the time. You swap parts afterwards if you want a specific one; the swap is two clicks.

Each part keeps its deck name as a visible label, so r1 and c1 are findable on the board. Ground and the supply net route to the breadboard's power rails automatically (SPICE's node 0 is ground, and the importer works out which net is the positive rail); the other nodes arrive as ordinary numbered nets, ready for the rename pencil if you want the deck's names on your scope channels.

What gets rejected, by name

Some decks describe things the catalog cannot place yet, and the importer's policy is to refuse loudly rather than approximate silently: an I card (current source), a P-channel JFET model, or a K card (coupled inductors) rejects the import with the element named, because half a deck on the canvas looks like it should work, which is worse than none. Imports cap at 40 components and 40 nets, a teaching-circuit ceiling rather than a SPICE-workstation one. And one classic gotcha the error message will remind you of: SPICE treats the first line of a deck as its title, so a netlist whose first line is an element silently loses that element. Give your deck a title line, as the example above does.

This is an importer, not a SPICE IDE: there is no netlist editing inside de:volt, no .tran card execution, no export back to SPICE. You bring the circuit; the simulator brings the bench.

Why we think this matters for teaching

A netlist is unbeatable as an archival format and unreadable as a first encounter. The importer lets you hand students the canonical deck from the textbook and have them meet it as a physical-looking board with parts they can touch, probe, and break. Work the problem in both directions: read the netlist and predict the board, or study the board and reconstruct the netlist. The mapping between the two is most of what "reading a schematic" means.

The same dialog's other formats were covered earlier this week in the exports post. Details and supported-card notes live at docs.devoltapp.com/user/exporting. Tomorrow: the Environment panel, and the two humble parts that turn sunlight and weather into voltages.